Operating method of a non-volatile memory

ABSTRACT

A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of an application Ser. No. 11/162,116,filed on Aug. 29, 2005, now allowed, which claims the priority benefitof Taiwan application serial no. 94103338, filed on Feb. 3, 2005. Theentirety of each of the above-identified patent applications is herebyincorporated herein by reference and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a structure, a fabricationmethod and an operation method for a memory cell. More particularly, thepresent invention relates to a structure, a fabrication method and anoperation method for a non-volatile memory cell.

2. Description of Related Art

Due to the advantages of multiple data writing, reading, erasing and thestored data are retained even after the power is disconnected, thenon-volatile memory has been widely applied to personal computers andelectronic equipments.

A conventional non-volatile memory includes a floating gate and acontrol gate, which are made from polysilicon. While performing theprogramming or the erasing process on the non-volatile memory, biasvoltages are applied to the source region, the drain region and thecontrol gate, respectively, to inject electrons into the floating gate,or to pull electrons out from the floating gate. Conventionally, theinjection of charges for the non-volatile memory includes the channelhot-electron injection (CHEI) mode and the Fowler-Nordheim Tunnelingmode. Further, the modes for the programming and the erasing processesvary according to the methods for charge injection and ejection.

FIG. 1 illustrates a schematic cross-sectional view showing thestructure of a conventional non-volatile memory. This non-volatilememory includes an n-type substrate 100, a p-type deep well region 102,an n-type well region 104, gate stacked structures 106 a and 106 b, an ntype source region 108 a, an n-type drain region 108 b, a p-type shallowdoped region 109, a p-type pocket doped region 110 and a plug 112.Accordingly, the p-type deep well region 102 is located in the substrate100, the n-type well region 104 is allocated in the p-type deep wellregion 102. The gate stacked structures 106 a and 106 b are formed with,sequentially from the substrate 100, the tunnelling layer 114, thefloating gate 116, the gate dielectric layer 118, the control gate 120and the mask layer 122. Further, spacers 124 are disposed on thesidewalls of the gate stacked structures 106 a and 106 b. The n-typesource region 108 a is disposed in the n-type well region 104 and thep-type shallow doped regions 109 between two stacked gate structures 106a and 106 b. The p-type shallow doped region 109 is disposed in then-type well region 104 and contiguous to the surface of the substrate.The p-type pocket doped region 110 is disposed at the periphery of thetwo stacked gate structures 106 a and 106 b, and is extended to theundersides of the stacked gate structures 106 a and 106 b contiguous toa neighbouring p-type shallow doped region 109. Furthermore, the n-typedrain region 108 b is disposed in p-type pocket doping region 110 at theperiphery of the stacked gate structures 106 a and 106 b. The conductingplug 112 is disposed on the substrate 100 and penetrates through then-type drain region 108 b and a portion of the p-type pocket dopedregion 110.

However, while voltages are applied to the source region, the drainregion and the control gate layer to perform the programming process ona memory cell of the previously mentioned non-volatile memory, such as,a memory cell constituted with the stacked gate structure 106 a or 106b, the non-selected memory cells are affected by the applied voltagesfor the programming process. This is due to the fact that the controlgate and the source region of the selected memory cell are connected tothe control gate and the source region of a neighbouring cell through ashared word line and a shared source line. Consequently, the reliabilityof the memory devices is compromised.

Besides, while performing the above mentioned programming process for anon-volatile memory, the current leakage easily occurs due to thepresence of the source region, and the short distance between the sourceregion and control gate.

SUMMARY OF THE INVENTION

Generally speaking, the present invention is directed to provide anon-volatile memory for obviating any influence between neighboringmemory cells due to an application of voltage on a selected memory cellduring a programming operation.

In accordance to one aspect of the present invention, a fabricationmethod of a non-volatile memory is provided to prevent any influencebetween neighboring memory cells due to an application of voltage on aselected memory cell during a programming operation.

In accordance to another aspect of the present invention, an operationmethod of a non-volatile memory is provided to prevent any influencebetween the memory cells due an application of voltage on a selectedmemory cell during a programming operation.

Accordingly, the present invention is directed to provide a non-volatilememory, which includes a substrate, a plurality of trench isolations, afirst conducting type well region, a second conducting type shallowdoped region, a pair of stacked gate structures, two second conductingtype pocket doped region, two first conducting type drain region, anauxiliary gate layer, a gate dielectric layer and at least twoconducting plugs. The trench isolating structure is disposed in thesubstrate to define the active area. The first conducting type wellregion is disposed in the substrate and the second conducting typeshallow doped region is disposed in the first conducting type wellregion and is contiguous to the surface of the substrate. The pairedstacked gate structures are disposed in the active region above thesubstrate and beside the side of each trench isolation structure.Furthermore, the stacked gate structure includes at least a floatinggate layer and a control gate layer disposed above the floating gatelayer second conducting type pocket doped regions are disposed in thesubstrate at the peripheries of the paired stacked gate structures andare extended to the underside of the stacked gate structures,respectively. The first conducting type drain regions are disposed inthe pocket doped region at the peripheries of the paired stackedstructures. The auxiliary gate layer is disposed between the stackedgate structures and on the substrate, and the bottom of the auxiliarygate layer is lower than the bottom of the second conducting typeshallow doped region. The gate dielectric layer is disposed at leastbetween the auxiliary gate layer and the substrate, and between theauxiliary gate layer and each stacked gate structure. There are at leasttwo conducting plugs disposed in the substrate, and the conducting plugsextend downward to connect with the pocket doped region and the drainregion, which is in the pocket doped region.

According to an embodiment of the present invention for the abovementioned non-volatile memory, the substrate is, for example, a firstconducting type substrate.

According to an embodiment of the present invention for the abovementioned non-volatile memory, the second conducting type deep wellregion is further disposed in the substrate, and the first conductingwell region is disposed in the second conducting type deep well region.

According to an embodiment of the present invention for the abovementioned non-volatile memory, the stacked gate structure issequentially stacked by a tunnelling layer, the floating gate layer, thegate dielectric layer and the control gate layer on the substrate.

According to an embodiment of the present invention for the abovementioned non-volatile memory, the materials for the above mentionedauxiliary gate layer, the floating gate layer or the control gate layercan be, for example, polysilicon or doped silicon.

According to an embodiment of the present invention for the abovementioned non-volatile memory, the materials for the above mentionedgate dielectric layer can be, for example, silicon oxide.

According to an embodiment of the present invention for the abovementioned non-volatile memory, the memory array can be a NOR memoryarray.

According to an embodiment of the present invention for the abovementioned non-volatile memory, the first conducting type can be ann-type and the second conducting type can be a p-type.

According to an embodiment of the present invention for the abovementioned non-volatile memory, the auxiliary gate layer is disposed ontrench isolation structure.

In accordance to yet another aspect of the present invention, thenon-volatile memory can employ the auxiliary gate layer to control theinduction of the source region. By applying the appropriate auxiliarygate voltage to control the induction of the source region, the currentleakage of the devices which often occurs in the conventionalprogramming process, can be prevented. In addition, the selected memorycells will not affect the neighbouring memory cells and the reliabilityof the devices is improved.

A fabrication method for the non-volatile memory of the presentinvention is provided and the method includes providing a substrate,forming a plurality of trench isolation structures to define the activeregion, followed by forming a first conducting type well region in thesubstrate, and forming a second conducting type shallow doped region inthe first conducting type well region and contiguous to the surface ofthe substrate. Thereafter, in the active region, at least a pair ofstacked structures is formed on the substrate, and each stacked gatestructure is disposed beside one side of each trench isolationstructure. The stacked gate structure includes at least a floating gatelayer and a control gate layer on the floating gate. Afterwards, in thesubstrate, two second conducting type of the pocket doped regions areformed at the peripheries of the stacked gate structures, and eachpocket doped region is further extended to the underside of each stackedgate structure. Thereafter, in the pocket doped region, a firstconducting type drain region is formed at the peripheries of the stackedgate structures. Then, a portion of each trench isolation structurebetween the paired stacked gate structures is removed for the surface ofthe trench isolation structure be lower than the bottom of the secondconducting type shallow doped region and form at least two trenches inthe substrate. Furthermore, a gate dielectric layer is formed on thesurface of the stacked gate structures and the exposed surface of thesubstrate. Between the two stacked gate structures, an auxiliary gatelayer is formed on the gate dielectric layer. In order to cover the gatedielectric layer and the auxiliary gate layer, a dielectric layer isformed on the substrate, and there are at least two contact windowsformed in the dielectric layer, which expose the drain region and aportion of the pocket doped region. Finally, a plurality of conductingplugs is formed in the contact windows.

According to an embodiment of the present invention for the abovementioned non-volatile memory, the method to remove a portion of theabove mentioned trench isolation structure can be, for example, aself-aligned etching process.

According to an embodiment of the present invention for the abovementioned fabrication method of the non-volatile memory, the substratecan be, for example, a first conducting type of substrate.

According to an embodiment of the present invention for the abovementioned fabrication method of the non-volatile memory, after theformation of the trench isolation structure and before the formation ofthe first conducting type well region, the second conducting type deepwell region is formed in the substrate and the first conducting typewell region is disposed in the second conducting type deep well region.

According to an embodiment of the present invention for the abovementioned fabrication method of the non-volatile memory, the stackedgate structure is sequentially stacked with a tunnelling layer, afloating gate layer, the gate dielectric layer and a control gate layeron the substrate.

According to an embodiment of the present invention for the abovementioned fabrication method of the non-volatile memory, the materialsfor the above mentioned auxiliary gate layer, the floating gate layer orthe control gate layer can be, for example, polysilicon or dopedsilicon.

According to an embodiment of the present invention for the abovementioned fabrication method of the non-volatile memory, the formationof the conducting plugs can be, for example, through a short circuit toconnect the drain region and the pocket doped region.

According to an embodiment of the present invention for the abovementioned fabrication method of the non-volatile memory, the firstconducting type can be an n-type and the second conducting type can be ap-type.

According to an embodiment of the present invention for the abovementioned fabrication method of the non-volatile memory, the auxiliarygate layer fills the above-mentioned two trenches.

In accordance to again another aspect of the present invention, thefabrication method of the non-volatile memory can employ the auxiliarygate layer to control the induction of the source region. By applyingthe appropriate auxiliary gate voltage to control the induction of thesource region, the current leakage of the devices which often occurs inthe conventional device can be prevented. In addition, the fabricationmethod of the present invention is compatible with the conventionalmethod; therefore, there is no extra spending for equipments.

An operation method for a non-volatile memory of the present inventionis provided; in particular, this operation method can be applied to theabove mentioned non-volatile memory and the procedures includesselecting between the two stacked gate structures as a designated memorycell, applying a first voltage to the control gate layer of the selectedmemory cell during a programming process. The operation method furtherincludes applying a second voltage to the drain region disposed besidethe side of the selected memory cell and the first conducting type wellregion; and applying a third voltage to the auxiliary gate layer and thesecond conducting type deep well region to perform the programming onthe selected memory cell. The first voltage can be ranged between −5 and−15 volts, for example; the second voltage can be ranged between 1 and10 volts, for example; and the third voltage can be, for example, 0volt.

According to an embodiment of the present invention for the abovementioned fabrication method of the non-volatile memory, in order toperform an erasing process for the selected memory cell, the operationmethod further includes applying a fourth voltage on the control gatelayer of the selected memory cell; applying a fifth voltage on the firstconducting well region and the second conducting deep well region; andsetting the drain region disposed at the side of the memory cell and theauxiliary gate layer at floating. The fourth voltage can be rangedbetween 5 and 15 volts, for example; and the fifth voltage can be rangedbetween −5 and −15 volts, for example.

According to an embodiment of the present invention for the abovementioned fabrication method of the non-volatile memory, in order toperform a reading process on the selected memory cell, the operationmethod further includes applying a sixth voltage to the control gatelayer of the selected memory cell and the auxiliary gate layer; placinga seventh voltage on the first conducting well region; and applying aneighth voltage to the drain region disposed at the side of the selectedmemory cell and the second conducting type deep well region. Inaddition, the sixth voltage can be, for example, ranged between 1 and 10volts; the seventh voltage can be ranged between 1 and 10 volts, forexample; and the eighth voltage can be, for example, 0 volt.

In accordance to a further aspect of the present invention, theoperation method of the non-volatile memory can employ the auxiliarygate layer to control the induction of the source region. By applyingthe appropriate auxiliary gate voltage to control the induction of thesource region, the current leakage of the devices, which often occurs inthe conventional programming operation, can be prevented. In addition,the selected memory cells will not affect other neighbouring memorycells and the reliability of the devices is improved.

It is to be understood that the foregoing general description and thefollowing detailed description with attached figures are exemplary andexplanatory for the objects, specification and merits of the presentinvention only, and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic cross sectional view of a conventionalnon-volatile memory.

FIG. 2 is a schematic, top view diagram of a non-volatile memoryaccording to an embodiment of the present invention.

FIG. 3A is a schematic, cross sectional view (X direction) diagram of anon-volatile memory along the cutting line I-I′ in FIG. 2 according toan embodiment of the present invention.

FIG. 3B is a schematic, cross sectional view (Y direction) diagram of anon-volatile memory along the cutting line II-II′ in FIG. 2 according toan embodiment of the present invention.

FIG. 4 is a schematic, cross sectional view diagram of a non-volatilememory according to an embodiment of the present invention.

FIG. 5A to FIG. 5D are the schematic, cross sectional views (Xdirection) diagrams of FIG. 2 along the cutting line I-I′ showing thesteps for the fabrication method of the non-volatile memory.

FIG. 6A to FIG. 6D are the schematic, cross sectional view (Y direction)diagrams of FIG. 2 along the cutting line II-II′ showing the steps forthe fabrication method of the non-volatile memory.

FIG. 7 is a schematic diagram illustrating the equivalent circuit chartof a NOR memory array according to an embodiment of the presentinvention.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

In the following embodiment, the first conducting type is an n dopanttype and the second conducting is a p dopant type. However, as isobvious to one ordinarily skilled in the art, the above mentionedconducting type can be switched, and, the alternative embodiment willnot be described in detail herein. In addition, the presented embodimentapplies a shared auxiliary gate layer of a NOR type non-volatile memoryto illustrate the invention.

FIG. 2 is a schematic, top view diagram of a non-volatile memoryaccording to an embodiment of the present invention. FIG. 3A is a crosssectional view (X direction) diagram of a non-volatile memory along thecutting line I-I′ in FIG. 2 according to an embodiment of the presentinvention. FIG. 3B is a schematic, cross sectional view (Y direction)diagram of a non-volatile memory along the cutting line II-II′ in FIG. 2according to an embodiment of the present invention.

Please referring to FIG. 2, FIG. 3A and FIG. 3B concurrently, thenon-volatile memory of the present invention includes at least an n-typesubstrate 200, a p-type deep well region 202, an n type well region 204,a p-type shallow pocket doped region 206, at least two stacked gatestructures 208 a and 208 b, two p-type pocket doped regions 210 a and210 b, two n-type drain regions 212 a and 212 b, an auxiliary gate layer214, a gate dielectric layer 216, at least two conducting plugs 218 aand 218 b, and a trench isolation structure 220.

The trench isolation structure 220 is disposed in the substrate 200 todefine the active region 222. In addition, the p-type deep well region202 is disposed in the substrate 200. Further, the n type well region204 is disposed in the p-type deep well region 202, while the p-typeshallow doped region 206 is disposed in the n-type region 204 and iscontiguous to the surface of the substrate 200.

Moreover, a paired of stacked gate structures 208 a and 208 b isdisposed on the substrate 200 in the active region 222 beside the sideof each trench isolation structure 220. Each stacked gate structure 208a and 208 b is stacked sequentially with a tunnel layer 224, a floatinggate layer 226, a gate dielectric layer 228 and a control gate layer 230on the substrate 200. In one embodiment, the stacked gate structures 208a and 208 b are further including a mask layer 232 disposed on thecontrol gate layer 230. In addition, the material for the floating gate226 is selected from the group consisting of polysilicon, doped siliconand other appropriate materials. In the same manner, the material forthe control gate 230 is selected from the group consisting ofpolysilicon, doped silicon and other appropriate material.

Additionally, the p-type pocket doped regions 210 a and 210 b arerespectively disposed at the periphery of the paired of stacked gatestructures in the substrate 200, and the pocket doped regions 210 a and210 b are further extended respectively to the underside of each stackedgate structure 208 a and 208 b. The n-type drain regions 212 a and 212 bare respectively disposed in the p-type pocket doped regions 210 a and210 b at the peripheries of the stacked gate structures 208 a and 208 b.

Further, the auxiliary gate layer 214 is disposed on the substrate 200between the two stacked gate structures 208 a and 208 b and in a portionof the trench isolation structure 220, wherein the bottom of theauxiliary gate layer 214 is lower than the bottom of the p-type shallowdoped region 206. The material for the auxiliary gate layer 214 includespolysilicon, the doped polysilicon and other appropriate materials.

In addition, the gate dielectric layer 216 is at least disposed betweenthe auxiliary gate layer 214 and the substrate 200, and between theauxiliary gate layer 214 and the stacked gate structures 208 a and 208b. The material for the gate dielectric layer 216 can be, for example,silicon oxide. The conducting plugs 218 a and 218 b are disposed on thesubstrate 200; and conducting plug 218 a is further extended to connectthe drain region 212 a and the pocket doping region 210 a, while theconducting plug 218 b is extended to connect the drain region 212 b andthe pocket doping region 210 b.

According to the operation method of the non-volatile memory in thepresent invention, during the programming process, the auxiliary gatelayer is used to control the induction of the source region. By applyingthe appropriate auxiliary gate voltage to control the induction of thesource region, the current leakage of the devices, which often occurs inthe conventional programming operation, can be prevented. In addition,the selected memory cells will not affect other neighbouring memorycells during programming process. Accordingly, the reliability of thedevices is improved.

It is noteworthy to be mentioned that, according to the above embodimentof the present invention, only two stacked gate structures 208 a and 208b of the non-volatile memory are illustrated. However, the embodiment isnot intended to be limited by these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims. And, it is understandablethat the one skilled in the art can apply four stacked gate structures208 a, 208 b, 208 c, and 208 d for the invention. Even more stacked gatestructures which implies more memory cells can be applied. Therefore, ifevery two stacked gate structures are paired, for example, 208 a and 208b as a pair, and 208 c and 208 d as another pair, each pair will share apocket doped region, a drain region and a conducting plug.

The steps of the fabrication method of the above-mentioned non-volatilememory are illustrated by FIG. 5A˜5D and FIG. 6A 6D. FIG. 5A to FIG. 5Dare the schematic, cross sectional view (X direction) diagram of anon-volatile memory along the cutting line I-I′ in FIG. 2, while FIG. 6Ato FIG. 6D are the schematic, cross sectional view (Y direction)diagrams of FIG. 2 along the cutting line II-II′.

Referring to FIG. 2, FIG. 5A and FIG. 6A, the method involves providingan n-type substrate 200 which can be, for example, a silicon substrate.Thereafter, a plurality of trench isolation structures 220 is formed inthe substrate 200 to define the active region 222. The formation methodof the trench isolation structure 220 applies the conventional STIprocess.

Afterwards, a p-type deep well region 202 is formed in the substrate 200through the ion implantation process to implant the p-type doping. Then,a n-type well region 204 is formed in the p-type deep well region 202through the ion implantation process to implant the n-type doping.Thereafter, a p-type shallow doped region 206 is formed in the n-typewell region 204 and the p-type shallow doped region is contiguous to thesurface of the substrate 200. The p-type shallow doping region 206 isformed by performing ion implantation to implant the p-type dopants.

Continuing to FIG. 2, FIG. 5B and FIG. 6B, at least a pair of stackedgate structures 208 a and 208 b is formed on the substrate 200 of theactive region 222, and each stacked gate structure 208 a and 208 b isdisposed at the side of the each trench isolation structure 220. Thestacked gate structure 208 a and 208 b is formed by sequentiallystacking the tunnel layer 224, the floating gate layer 226, the gatedielectric layer 228 and the control gate 230 on the substrate 200. Thesteps for the formation of the stacked gate structures 208 a and 208 bincludes forming a tunnelling material layer (not shown in the figures)on the substrate 200, for example, through performing thermal oxidationon the substrate 200. A plurality of floating gate material layers isalso formed along the extension direction (X direction) of the trenchisolating structure 220. The material for the floating gate materiallayer includes polysilicon, doped polysilicon and other appropriatematerials. Then, a gate dielectric material layer (not shown in thefigures) is formed on the floating gate material layer, and the materialfor the gate dielectric material layer is, for example, silicon nitrideor stacked material like silicon oxide/silicon nitride/silicon oxide.Thereafter, a plurality of control gate layers 230 is formedperpendicular to the trench isolation structure 220, extended in Ydirection, and the material for the control gate layers 230 is selectedfrom a group of materials that include polysilicon, doped polysiliconand other appropriate material. Besides, the control gate layers 230 aredefined by a mask layer 232 having strips that extend along the samedirection as the control gate layers. Furthermore, portions of the gatedielectric material layer, the floating gate material layer and thetunnelling material layer which are not covered by the control gatelayer 230, are removed to form the gate stacked structures 208 a and 208b.

Afterwards, the p-type pocket doped regions 210 a and 210 b are formedin the substrate 200 at the peripheries of the pair of the stacked gatestructure 208 a and 208 b, respectively, and the p-type pocket dopedregions 210 a and 210 b are extended to the underneaths of the stackedgate structure 208 a and 208 b. The fabrication method of the p-typepocket doped regions 210 a and 210 b includes forming a mask layer (notshown in the Figures) between the stacked gate structures 208 a and 208b to cover the space between the two stacked gate layer 208 a and 208 b.Thereafter, the mask layer and the two stacked gate layers 208 a and 208b are used as an implantation mask to implant the p-type dopants. Adrive-in process is performed to complete the implantation process.

Moreover, in the pocket doped regions 210 a and 210 b, the n-type drainregions 212 a and 212 b are formed at the peripheries of the pairedstacked gate structures 208 a and 208 b. The fabrication method of then-type drain regions 212 a and 212 b includes forming a mask layer (notshown in the figures) between the stacked gate structures 208 a and 208b to cover the space between the stacked gate structures 208 a and 208b. The mask and the stacked gate structures 208 a and 208 b are used asimplantation mask implant n-type dopants, followed by conducting adrive-in process.

Referring to FIG. 2, FIG. 5C and FIG. 6C, a portion of each trenchisolation structure 220 disposed between the stacked gate structures 208a and 208 b is removed to enable the surface of the trench isolationstructure 220 lower than the bottom of the p-type doped region 206 toform at least two trenches 234 in the substrate 200. In particular, dueto the material difference between the trench isolation structure 220and the substrate 200, self-alignment is applied in removing the portionof each trench isolation structure.

Thereafter, a gate dielectric layer 216 is formed on the surface of theexposed substrate 200 and the stacked gate structures 208 a and 208 b.The fabrication method for the gate dielectric layer 216 can be, forexample, oxidation.

Afterwards, between the two stacked gate structures 208 a and 208 b, anauxiliary gate layer 214 is formed on the gate dielectric layer 216, andthe auxiliary gate layer 214 also fills the trench 234. The material ofthe auxiliary gate structure 214 is selected from a group consisting ofpolysilicon, doped polysilicon and other appropriate materials. Thefabrication method of the auxiliary gate layer 214 includes forming anauxiliary gate material layer (not shown in the figures), and performingthe lithography process and the etching process to define a plurality ofauxiliary gate layers that are extended in the Y direction,perpendicular to the trench isolation structure 220.

Referring next to FIG. 2, FIG. 5D and FIG. 6D, a dielectric layer 236 isformed on the substrate 200 to cover the auxiliary gate layer 214 andthe gate dielectric layer 216, and there are at least two contact windowopenings 238 a and 238 b formed in the dielectric layer 236. The contactwindow opening 238 a exposes the drain region 212 a and a portion of thepocket doped region 210 a. Concurrently, the contact window opening 238b exposes the drain region 212 b and a portion of the pocket dopedregion 210 b. The material for the dielectric layer 236 is selected fromthe group consisting of silicon oxide, silicon oxygen nitride and otherappropriate materials. The fabrication method for the dielectric layer236 includes forming a dielectric material layer on the substrate 200,followed by defining the contact window opening 238 a and 238 b throughthe lithography process and the etching process.

Moreover, a plurality of conducting plugs 218 a and 128 b are formed inthe contact window openings 238 a and 238 b, respectively. Theconducting plug 218 a is connected to the drain region 212 a and thepocket doped region 210 a through short circuit, while the conductingplug 218 b is connected to the drain region 212 b and the pocket dopedregion 210 b through short circuit. The material for the conductingplugs is selected from the group consisting of tungsten and otherappropriate conducting material. The fabrication method for theconducting plugs includes filling the contact window openings 238 a and238 b with the conducting material, followed by performing chemicalmechanical polishing or back etching to remove the conducting materialoutside the contact window openings 238 a and 238 b.

In accordance with the fabrication method of the non-volatile memory forthe present invention, the auxiliary gate layer is applied to controlthe induction of the source region during the programming process. Byapplying the appropriate auxiliary gate voltage to control the inductionof the source region, the current leakage of the devices which oftenoccurs in the conventional programming operation, can be prevented dueto no induction of the source region. In addition, the fabricationmethod of the present invention is compatible with the conventionalmethod; therefore, there is no extra spending for equipments isrequired.

The programming, erasing and reading processes for a NOR typenon-volatile memory will be presented.

FIG. is a schematic diagram illustrating the equivalent circuit chart ofa NOR memory array according to an embodiment of the present invention;Table 1 records the voltages applied during an actual operation.However, the recorded voltage in table 1 is an example and is notintended to limit the invention.

Referring to FIG. 7, a plurality of memory cells Qn1˜Qn8 arranged in a4*2 array is presented. Also shown in FIG. 7, the selected word lines(WL) connected to the vertical column of memory cells and thenon-selected word lines (WLx) are presented. According to the embodimentof the present invention, the selected word lines (WL) connects, forexample, the control gate layer of the memory cells Qn3 and Qn4 alongthe same column; while the non-selected word lines (WLx) connects, forexample, the control gate layer of the memory cells Qn1 and Qn2 (ormemory cells Qn5 and Qn6, or memory cells Qn7 and Qn8) in the samecolumn. The source line (SL) connects the first conducting well regions(ex: n-type well region 204) along the same columns of the memory cellsand the source line (SL) is shared by two rows of neighboring memorycells. In accordance to the embodiments of the present invention, thesource line (SL) is, for example, the first conducting well region thatconnects the memory cells Qn3 and Qn4 in the same column, and twoneighboring memory cells Qn1 and Qn3 which are along the same row sharethe first conducting well region. The auxiliary gate line AG of theauxiliary gate layer connects the memory cells in the same column, andtwo horizontal rows of neighboring memory cells share the same auxiliarygate line AG. In accordance to the embodiments of the present invention,the auxiliary gate line AG is, for example, the auxiliary gate layersthat connect the memory cells Qn3 and Qn4 along the same column, and thetwo neighboring memory cells Qn1 and Qn3 along the same row share thesame auxiliary gate line AG. Regarding the selected bit line (SBL)memory cell and the non-selected bit line (SBLx), according to theembodiment of the present invention, the selected bit line (SBL) is, forexample, the drain regions that connect the memory cells Qn1, Qn3, Qn5and Qn7 along the same row, while the non-selected bit line (SBLx) is,for example, the drain regions that connect the memory cells Qn2, Qn4,Qn6 and Qn8 along the same row. TABLE 1 programming erasing readingselected word −10 volts 10 volts 3.3 volts lines (WL) non-selected −2volts 10 volts 0 volts word lines (WLx) selected bit 6 volts Floating(F) 0 volts line (SBL) non-selected 0 volts Floating (F) Floating (F)bit line (SBLx) Source line (SL) 6 volts −6 volts 1.65 volts (n-typewell region 204) auxiliary gate 0 volts Floating (F) 3.3 volts line AGp-type deep 0 volts −6 volts 0 volts well region (202)

Please referring to FIG. 4, FIG. 7 and Table 1, in order to eject thecharges from the floating gate layer 226 through F-N tunneling modeduring the programming operation of the non-volatile memory in thepresent invention, a first voltage is applied to the control gate 230 ofthe selected memory cell (ex: 208 b in the FIG. 4 and Qn3 in the FIG.7), a second voltage is applied to the drain region 212 b at the side ofthe selected memory cell and the n-type well region 204, a third voltageis applied to the auxiliary gate layer 214 and the p-type deep wellregion 202. In addition, during the programming process, a fourthvoltage is applied to the control gate layers of the neighboring memorycells, and a fifth voltage is applied to the bit lines (drain region) ofthe neighboring memory cells. In an embodiment of the present invention,the above mentioned first voltage ranges between −5 and −15 volts, forexample,; the second voltage ranges between 1 and 10 volt, for example;the third voltage is, for example, 0 volt; the fourth voltage rangesbetween −1 and −10 volts, for example; the fifth voltage is, forexample, 0 volts. In the embodiment of the present invention, the firstvoltage is, for example, −10 volts; the second voltage is, for example,6 volts; the third voltage is, for example, 0 volt; the fourth voltageis, for example, −2 volts; the fifth voltage is, for example, 0 volt.

In particular, according to the present invention, the auxiliary gatelayer is applied to induce the source region during the programmingprocess. Depending on the applied auxiliary gate voltage, there can beno induction of the source region. Therefore, the selected memory cellwill not affect the neighbouring memory cells, and the reliabilitydevice is improved. In addition, the current leakage problem for thedevices is prevented.

Besides, during the erasing operation, a sixth voltage is applied to thecontrol gate layer 230 of the selected memory cell (ex: 208 b in theFIG. 4 and Qn3 in the FIG. 7) of the above mentioned non-volatile memoryin the present invention, a seventh voltage is applied to the n-typewell region 204 and p-type deep well region 202, and the drain region212 b at the side of the selected memory cell and the auxiliary gatelayer 214 are set at floating for charges to be injected into thefloating gate layer 226 through the F-N tunneling mode. Besides, duringthe erasing operation, the control gate layers of the neighboring memorycells is applied with the same voltage as the control gate layer of theselected memory cell. Furthermore, the bit line (drain region) of theneighboring memory cells is set at floating. In an embodiment of thepresent invention, the above mentioned sixth voltage ranges between 5and 15 volts, for example,; the seventh voltage ranges between −5 and−15 volts, for example. In the embodiment of the present invention, thesix voltage is, for example, 10 volts; and the seventh voltage is, forexample, −6 volts.

Moreover, during the reading operation, an eighth voltage is applied tothe control gate layer 230 of the selected memory cell (ex: 208 b in theFIG. 4 and Qn3 in the FIG. 7) and the auxiliary gate layer of the abovementioned non-volatile memory in the present invention, a ninth voltageis applied to the n-type well region 204, a tenth voltage is applied tothe drain region 212 b at the side of the selected memory cell and thep-type deep well region 202, an eleventh voltage is applied to thecontrol gate of the neighboring memory cells during the readingoperation. In addition, the control gate of the neighboring memory cells(drain regions) is set at floating. In an embodiment of the presentinvention, the above mentioned eighth voltage ranges between 1 and 10volts, for example; the ninth voltage ranges between 1 and 10 volts, forexample; the tenth voltage is, for example, 0 volt; the eleventh voltageis, for example, 0 volt. In the embodiment of the present invention, theeighth voltage is, for example, 3.3 volts; the ninth voltage is, forexample, 1.65 volts; the tenth voltage is, for example, 0 volt; and theeleventh voltage is, for example, 0 volt.

Although there is no source region disposed in the memory cell of thepresent invention, the source region can be induced by applying avoltage to the auxiliary gate layer to form a source inversion layer,which is also known as the virtual source line. Therefore, the readingoperation can be performed through the formation of the virtual sourceline.

In accordance to the present invention, the auxiliary gate layer isapplied to control the induction of the source region during theprogramming process. By applying the appropriate auxiliary gate voltage,the source region is not induced, and the current leakage for thedevices is prevented. Further, the selected memory cell will not affectthe neighbouring memory cells. Besides, in order to perform the readingprocess, the virtual source line can be generated by applying a voltageto the auxiliary gate layer to perform the reading operation.

It will be apparent that the above mentioned description with attachedfigures are exemplary and explanatory for the objects, specification andmerits of the present invention only, and are not restrictive of theinvention, those skilled in the art that various modifications andvariations can be made to the present invention without departing fromthe scope or spirit of the invention. In view of the foregoing, it isintended that the present invention cover modifications and variationsof this invention provided they fall within the scope of the followingclaims and their equivalents.

1. An operation method for a non-volatile memory, wherein the operationmethod is suitable for the non-volatile memory comprising at least asubstrate, a plurality of trench isolation structures disposed in thesubstrate, a first conducting type well region disposed in thesubstrate, and a second conducting type shallow doped region disposed inthe first conducting type well region and contiguous to a surface of thesubstrate, a pair of stacked gate structures disposed at a side of eachtrench isolation structure, wherein each stacked gate structurecomprises at least a floating gate and a control gate on the floatinggate, two second conducting type pocket doped regions in the substrateand at peripheries of the pair of stacked gate structures, two firstconducting type drain regions disposed in each pocket doped region andat the peripheries of the pair of the stacked gate structures, anauxiliary gate layer disposed on the substrate and between the twostacked gate structures, wherein a bottom of the auxiliary gate layer islower than a bottom of the second conducting type shallow doped region,the operation method comprises: selecting a memory cell in the pair ofstacked gate structures; and while performing a programming process,applying a first voltage on the control gate layer of a selected memorycell, applying a second voltage on the drain region and the firstconducting type well region at a side of the selected memory cell, andapplying a third voltage on the auxiliary gate layer and the secondconducting type deep well region to program the selected memory cell. 2.The operation method for the non-volatile memory as recited in claim 1,wherein the first voltage ranges between −5 and −15 volts, the secondvoltage ranges between 1 and 10 volts, and the third voltage is 0 volt.3. The operation method for the non-volatile memory as recited in claim1, while performing an erasing process, the operation method furthercomprising: applying a fourth voltage on the control gate layer of theselected memory cell, applying a fifth voltage on the first conductingwell region and the second conducting deep well region, and setting thedrain region at the side of the selected memory and the auxiliary gatelayer at floating to erase the selected memory cell.
 4. The operationmethod for the non-volatile memory as recited in claim 3, wherein thefourth voltage ranges between 5 and 15 volts and the fifth voltageranges between −5 and −15 volts.
 5. The operation method for thenon-volatile memory as recited in claim 1, while performing a readingprocess, the operation method further comprising: applying a sixthvoltage on the control gate layer and the auxiliary gate layer of theselected memory cell, applying a seventh voltage on the first conductingtype well region, and applying an eighth voltage on the secondconducting type deep well region and the drain region at the side of theselected memory to read the selected memory cell.
 6. The operationmethod for the non-volatile memory as recited in claim 5, wherein thesix voltage ranges between 1 and 10 volts, the seven voltage rangesbetween 1 and 10 volts, and the eighth voltage is 0 volt.